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Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls
Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls
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机译:在没有管道停顿的情况下,在管道浮点单元中舍入非正规数
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摘要
For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number. In one embodiment, the system includes: (1) a bit mask decoder that produces a bit mask that is a function of a precision of the denormalized number and an extent to which the denormalized number is denormal and (2) combinatorial logic, coupled to the bit mask decoder, that performs logical operations with respect to a fraction portion of the denormalized number, the bit mask and at least one shifted version of the bit mask to yield the L, R and S bits.
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