Data output buffer circuit usable with both PCI and PCI-X buses

摘要

Disclosed is a data processing system comprising a control unit for receiving data from a main core and outputting given control signals, a level shifter for amplifying the electric potential of said given control signals and outputting corresponding driving signals, a data output buffer for receiving said driving signals from said level shifter and outputting a driving voltage having a voltage range defined in the PCI or/and PCI-X specifications, to an input/output pad, and said data output buffer being in a high impedance state to prevent a PCI mode voltage inputted to said pad from being leaked to a power source terminal when said data processing system is operated in PCI mode.