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Circuit and method for reducing quiescent current in a voltage reference circuit

机译:降低电压基准电路中静态电流的电路和方法

摘要

A voltage reference circuit capable of operating at reduced quiescent currents is described. The voltage reference circuit comprises an output circuit, a timer circuit and a control circuit. When in standby mode, in order to decrease power consumed by the output circuit, current through the output circuit is decreased, allowing the voltage at the output node to fall outside of a desired range. To determine when this event has occurred, the control circuit includes a test circuit that generates a test signal characterized by having a voltage that is correlated with the voltage at the output terminal.
机译:描述了一种能够在减小的静态电流下工作的电压基准电路。参考电压电路包括输出电路,定时器电路和控制电路。在待机模式下,为了减少输出电路消耗的功率,流经输出电路的电流将减小,从而使输出节点处的电压降至所需范围之外。为了确定何时发生该事件,控制电路包括测试电路,该测试电路生成测试信号,该测试信号的特征在于具有与输出端子处的电压相关的电压。

著录项

  • 公开/公告号US6545530B1

    专利类型

  • 公开/公告日2003-04-08

    原文格式PDF

  • 申请/专利权人 LINEAR TECHNOLOGY CORPORATION;

    申请/专利号US20010010398

  • 发明设计人 MARK G. JORDAN;

    申请日2001-12-05

  • 分类号G05F11/00;

  • 国家 US

  • 入库时间 2022-08-22 00:04:21

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