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Circuit and method for reducing quiescent current in a voltage reference circuit
Circuit and method for reducing quiescent current in a voltage reference circuit
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机译:降低电压基准电路中静态电流的电路和方法
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摘要
A voltage reference circuit capable of operating at reduced quiescent currents is described. The voltage reference circuit comprises an output circuit, a timer circuit and a control circuit. When in standby mode, in order to decrease power consumed by the output circuit, current through the output circuit is decreased, allowing the voltage at the output node to fall outside of a desired range. To determine when this event has occurred, the control circuit includes a test circuit that generates a test signal characterized by having a voltage that is correlated with the voltage at the output terminal.
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