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Device modeling and characterization structure with multiplexed pads

机译:具有多路复用焊盘的器件建模和表征结构

摘要

A multiplexed transistor characterization and modeling structure for testing a plurality of transistors, The characterization and modeling structure comprises a common substrate pad, a common source pad, a plurality of drain pads, and a plurality of gate pads. The characterization and modeling structure further comprises a plurality of individual transistors. Each individual transistor comprises a substrate connected to the common substrate pad, a source connected to the common source pad, a drain connected to a single drain pad, and a gate connected to a single gate pad, wherein each individual transistor is connected to a different drain pad and gate pad combination.
机译:一种用于测试多个晶体管的多路复用晶体管表征和建模结构。该表征和建模结构包括公共基板焊盘,公共源极焊盘,多个漏极焊盘和多个栅极焊盘。表征和建模结构还包括多个单独的晶体管。每个单独的晶体管包括连接到公共衬底焊盘的衬底,连接到公共源极焊盘的源极,连接到单个漏极焊盘的漏极和连接到单个栅极焊盘的栅极,其中每个单独的晶体管连接到不同的晶体管漏极焊盘和栅极焊盘的组合。

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