Method for timing analysis during automatic scheduling of operations in the high-level synthesis of digital systems

摘要

A design-timing-determination process for an electronic design automation system approximates the timing of a whole design quickly and on-the-fly. Such allows a scheduling system to construct operation schedules that are ultimately realizable. A timing analysis is applied each time an individual operation is scheduled, and may be called many times to get a single operation scheduled. A graph representing combinational logic is partitioned into a collection of logic trees with nodes that represent gates and terminals, and arcs that represent connections. A compacted model of each logic tree is constructed by replacing them with equivalent trees having no interior nodes. The timing of the original circuit is analyzed along each path from the leaves to the roots. A propagation delay for each path is determined, and such is annotated onto each corresponding arc of the simplified tree. Any dependency of the propagation delay in the original circuit on the slew rate of their input signals is annotated onto the corresponding leaf of the simplified tree. Capacitive loads can also be copied from the logic-tree leaves and annotated on the simplified-tree leaves. Any load/delay response curves of the output gate at the apex of the logic tree and is copied to the root of the simplified tree. The entire delay calculation is collapsed into a simple edge-weighted longest-path traversal, and is much simpler than trying to compute the slew rates and delays for each cell in a circuit.