PHASE AND GENERATOR BASED SOC DESIGN AND/OR VERIFICATION

摘要

An EDA tool suite is equipped with the ability to responsively invoke a chain of one or more generators corresponding to one or more phases of a design/verification process to process to process design information of IP blocks forming a SOC design to transform the design information, as a result of each invocation, from one state to another state. In one embodiment, the phases may be one or more of a design generation phase, a simulation hardware logic generation phase, an embedded/diagnostic software generation phase, and a verification environment configuration script generation phase.