When developing an ARM-based system-on-chip (SoC) design for wireless, mobile or PDA applications, designers integrate many various components in a relatively short amount of time-because time-to-market is critical. But, how can they verify their design will work correctly? Such a design might incorporate multiple AHB buses, multiple APB buses and a DSP sub-system. Since every component is connected to one of the AHB/APB buses, a good method of functional verification is a divide-and-conquer approach. Here, verification hotspots (parts of the design that are difficult to verify) are identified ahead of time. For each hot spot, assertion-based verification methodology is applied to ensure the components' functional correctness. Both static and dynamic formal verification approaches are used. A divide-and-conquer verification methodology relaxes the critical path in the verification test plan. As the project progresses, developers set up verification templates. As a bonus, these verification templates can be reused, just as circuit designs reuse basic components and peripherals.
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