Power MOS-gated device with recessed gate and method for its fabrication

摘要

A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n+ type region (31), the impurity concentration of which is caused to be 1 x 1019 cm-3 or more, is formed in an n- type semiconductor layer (2). By means of this, defects (61, 62) occur within the n+ type region (31) or in a proximity of the boundary of the n+ type region (31) and the n- type semiconductor layer (2). The defects (61) and (62) trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor layer (2) surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed.