DRAM WITH INTEGRAL SRAM AND SYSTEMS AND METHODS USING THE SAME

摘要

A memory (400) comprises a plurality of banks (401) and global access control circuitry (406). Each of the plurality of banks includes first and second arrays (506, 402) of memory cells, first accessing circuitry (413, 507) for selectively accessing cells in the first array in response to address bits, and second accessing circuitry (404, 413) for selectively accessing cells in the second array in response to address bits. Storage circuitry (502) within each bank (401) stores previously received address bits. Circuitry for comparing (503) within each bank compares received address bits with stored address bits in storage circuitry (503), with first accessing circuitry (413, 507) accessing cells in first array (506) addressed by the stored address bits when stored address bits and received address bits match and second accessing circuitry (404, 413) accessing cells in second array (402) addressed by the received address bits when the stored address bits and received address bits differ. Global access control circuitry (406) enables comparison of the stored address and the received address in a selected one of the plurality of banks (401).