A method and apparatus for generating a solid state circuit layout with in-design variability associated to the setting of analog signal processing parameters

摘要

A Solid State Integrated Circuit Layout is generated by specifying an intended functionality assortment and translating the functionality assortment into various circuitry representations. The circuitry representations are converted into circuit items of an overall circuit, whilst configuring both first interfaces between interacting circuit items within the overall circuit and also second interfaces between further such circuit items and an external world in accordance with predetermined interface specifications. In particular, for a situation wherein various such circuit items represent respective analog and/or steppable values to be specified on the basis of a circuit item in question, the parameter is assigned exclusively to a single such circuit item as a building block. The building block in question gets assigned a sufficient amount of in-design resizability and/or on-chip movability in accordance with a prespecified redefinability value range for the parameter in question.