FEEDBACK CONTROL OF STRIP TIME TO REDUCE POST STRIP CRITICAL DIMENSION VARIATION IN A TRANSISTOR GATE ELECTRODE

摘要

A method for decreasing variations in gate electrode widths is provided. The method includes providing a wafer having a gate electrode formed thereon and an anti-reflective coating layer formed over at least a portion of the gate electrode. The gate electrode has a width. The width of the gate electrode is measured. A strip rate for a strip tool adapted to remove the anti-reflective coating is determined. The measured width of the gate electrode is compared to a target gate electrode critical dimension to determine an overetch time based on the strip rate. The operating recipe of the strip tool is modified based on the overetch time. A processing line includes a first metrology tool, a strip tool, and a process controller. The first metrology tool is adapted to measure the width of a gate electrode formed on a wafer. The gate electrode has an anti-reflective coating layer formed over at least a portion of the gate electrode. The strip tool is adapted to remove the anti-reflective coating. The process controller is adapted to determine a strip rate for the strip tool, compare the width of the gate electrode to a target gate electrode critical dimension to determine an overetch time based on the strip rate, and modify the operating recipe of the strip tool layer based on the overetch time.