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Apparatus and Method for Distribution Clock in Multiple Processing System based on Compact Peripheral Component Interconnect

机译:基于紧凑外围组件互连的多处理系统中分配时钟的装置和方法

摘要

PURPOSE: A device and a method for distributing clock of a compact PCI(Peripheral Component Interconnect) based multiprocessing system are provided to install a system board variably by minimizing the skew of the clock transferred from respective different slots even if position of the slot is varied. CONSTITUTION: A clock generator(11) generates the clock. A clock distributor(12) outputs the clock by distributing the clock applied from the clock generator(11). A plurality of variable delay lines(13a-13h) delays and transfers the clocks applied from the clock distributor(12), and varies the delay lines. A plurality of first buffers(14a-14g) switches the output to other slot for the clock applied through the variable delay lines(13a-13h). The second buffer(15) buffers and outputs the clock applied from the variable delay lines(13a-13h) for an internal use clock. A multiplexer(16) selects one from the clock applied from the second buffer(15) and other slot, and outputs it as the clock used inside of the board. A clock driver configuration logic(17) controls an operation of the variable delay lines(13a-13h), the first buffers(14a-14g), and the multiplexer(16).
机译:目的:提供了一种用于分配基于紧凑型PCI(外围组件互连)的多处理系统的时钟的设备和方法,以通过最小化从各个不同插槽传送的时钟的时滞(即使插槽位置发生变化)来可变地安装系统板。组成:时钟发生器(11)产生时钟。时钟分配器(12)通过分配从时钟发生器(11)施加的时钟来输出时钟。多个可变延迟线(13a-13h)延迟并传输从时钟分配器(12)施加的时钟,并且改变延迟线。多个第一缓冲器(14a-14g)将输出切换到用于通过可变延迟线(13a-13h)施加的时钟的另一时隙。第二缓冲器(15)缓冲并输出从可变延迟线(13a-13h)施加的用于内部使用时钟的时钟。多路复用器(16)从第二缓冲器(15)和其他插槽施加的时钟中选择一个,并将其作为板内部使用的时钟输出。时钟驱动器配置逻辑(17)控制可变延迟线(13a-13h),第一缓冲器(14a-14g)和多路复用器(16)的操作。

著录项

  • 公开/公告号KR20030056710A

    专利类型

  • 公开/公告日2003-07-04

    原文格式PDF

  • 申请/专利权人 LG ELECTRONICS INC.;

    申请/专利号KR20010086993

  • 发明设计人 JUNG SANG IK;

    申请日2001-12-28

  • 分类号G06F1/04;

  • 国家 KR

  • 入库时间 2022-08-21 23:46:41

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