As the clock frequency and chip size of high-performance microprocessors increase, it becomes increasingly difficult to distribute signals across the chip, due to increasing propagation delays and decreasing allowable clock skew. This dissertation presents the design, implementation, and feasibility of a wireless interconnect system for clock distribution. The system consists of transmitters and receivers with integrated antennas communicating via electromagnetic waves at the speed of light. A global clock signal is generated and broadcast by the transmitting antenna. Clock receivers distributed throughout the chip detect the signal using integrated antennas, amplify and divide it down to a local clock frequency, and buffer and distribute these signals to adjacent circuitry.; First, the design and implementation of CMOS receiver circuitry used for wireless interconnects is presented. A design methodology is developed for CMOS low not amplifiers and demonstrated with a 0.8-μm, 900-MHz amplifier achieving a 1.2-dB noise figure and a 14.5-dB gain. Amplifiers are also demonstrated at 7.4, 14.4, and 23.8 GHz, using 0.25-, 0.18-, and 0.10-μm technologies, respectively. A design methodology based on injection locking is developed for CMOS frequency dividers, and a programmable divider which limits clock skew is presented. Dividers operating up to 10, 15.8, and 18.8 GHz are demonstrated, implemented in 0.25-, 0.18-, and 0.10-μm technologies, respectively.; Results for the overall wireless interconnect system are then presented. System requirements (gain, matching, noise, linearity) for wireless clock distribution are derived, including specifications for signal-to-noise ratio versus clock jitter, and amplitude mismatch versus clock skew. Wireless interconnect systems are demonstrated for the first time using on-chip antenna pairs, clock receivers, and clock transmitters. The interconnects operate across 3.3 mm at 7.4 GHz, using a 0.25-μm technology, and across 6.8 mm at 15 GHz, using a 0.18-μm technology. Using the 6.8-mm, 15-GHz interconnect, a 25-ps clock skew and 6.6-ps peak jitter have been measured at 1.875 GHz for two receivers separated by ∼3 mm. Finally, the wireless interconnect system is analyzed in terms of power dissipation, synchronization, process variation, latency, and area. These results indicate the feasibility of an intra-chip wireless interconnect system using integrated antennas.
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