首页> 外国专利> Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate, and a memory array made thereby

Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate, and a memory array made thereby

机译:自对准形成具有掩埋源极线和浮栅的浮栅存储单元的半导体存储阵列的方法,以及由此制成的存储阵列

摘要

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.
机译:一种形成浮栅存储单元的阵列的方法,以及由此形成的阵列,其中每个存储单元包括形成在半导体衬底的表面中的沟槽,以及在其间形成有沟道区的源极区和漏极区。源极区域形成在沟槽下方,并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿着衬底表面水平延伸的第二部分。导电浮栅设置在沟槽中,与沟道区第一部分相邻并且与沟道区第一部分绝缘。导电控制栅极设置在沟道区第二部分上方并与沟道区第二部分绝缘。一块导电材料的至少下部设置在与浮动栅极相邻并与浮动栅极绝缘的沟槽中,并且可以电连接至源极区。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号