LOW LOSS INTEGRATED CIRCUIT WITH REDUCED CLOCK SWING

摘要

The present invention relates to integrated circuits with clock systems, in particular large-scale pipelined CMOS circuits. In order to reduce the total power loss as much as possible, specially connected driver stages SP and SN are provided in the clock driver circuit to generate a clock supply voltage V corresponding to a value of about 1/2 of the typical supply voltage VDD. . The advantage obtained by the present invention is that the degradation is relatively small, in particular with relatively large reductions in power loss.