Fault Tolerant Memory Controller Using Tightly Coupled Dual Controller Modules

摘要

The present invention relates to an error resistant memory controller using a tightly coupled dual controller module. Each controller module checks whether another controller module or cache module exists and, if present, shares all configuration information about the controller module and its accessories with each other. Configuration information may be entered into one or both of the controller modules, the information being dynamically shared. Each cache module is "locked" by a separate controller module to prevent another controller module from suddenly interfering with the contents of the cache of the other controller module. During the initialization process each controller module checks for the presence of the associated cache module and, if present, is immediately "locked" by the controller module. If a controller module fails or indicates a malfunction, the other controller module may disable or "delete" the failed controller module to reset and release any locks that may be on that cache module. If the cache module is a write cache, the surviving controller module can resume operation if the malfunctioning controller module is interrupted, and complete the remaining write process for the storage of the disabled controller module to complete any host computer data. Can prevent the loss. The controller module is allowed to reboot after another controller module has failed and a series of events are detected and recognized by the surviving controller module so that the failed other controller module is not disabled. Dual controller modules communicate asynchronously to verify that they are capable of operation, to exchange and verify configuration information, and to dynamically provide operational status.