SRAM USING DRAM CELL CAPABLE OF CONTROLLING REFRESH OPERATION OF THE DRAM

摘要

PURPOSE: An SRAM compatible memory device using a DRAM cell for controlling a refresh operation is provided to perform a normal operation by minimizing a delay time in a process for generating a normal operating signal. CONSTITUTION: An oscillation circuit(110) can be formed by a ring oscillator. The oscillation circuit(110) generates an oscillation signal(VOSC) to a refresh relay circuit(140). A pulse generator(120) receives an external address signal(ADDR) and generates a normal operating control signal(PPZ) to a normal operating signal activation circuit(130). The normal operating signal activation circuit(130) receives the normal operating control signal(PPZ), activates a normal operating signal(CEN), and provides the normal operating signal(CEN) to the refresh relay circuit(140). The refresh relay circuit(140) is used for masking the oscillation signal(VOSC) by using the normal operating signal(CEN).