METHOD FOR WAIT MODE DESIGN IN THE GATE ARRAY OF PLC

摘要

PURPOSE: A method for designing a wait mode of a gate array for an exclusive use of programmable logic controller(PLC) is provided to effectively control input and output of the PLC and specific modules and strong for electrical noise for variously set wait in the middle, in front of and behind a signal. CONSTITUTION: A first delay point flag is set to '1' in synchronization with low activation of a device selection signal and a first resistor set to a predetermined value performs down count to be "0". A second delay point flag is set to "1" in synchronization with low activation of a read or write signal and a second resistor set to a predetermined value performs down count to be "0". A third delay point flag is set to "1" in synchronization with high activation of the read or write signal and a third resistor set to a predetermined value performs down count to be "0". Delay numbers are differently set according to the respective delay time point so that the wait times become different.