首页> 外国专利> Implementing scrambler algorithms in processor-implemented data paths involves inter alia configuring data stream bit slice so data stream is combined with scrambler signal

Implementing scrambler algorithms in processor-implemented data paths involves inter alia configuring data stream bit slice so data stream is combined with scrambler signal

机译:在处理器实现的数据路径中实现加扰器算法尤其涉及配置数据流位片,以便将数据流与加扰器信号组合

摘要

The method involves controlling the data paths in each slice by the local multiplexer with the bit slice contained within it so that the data paths are represented by four units on one hand, and on the other hand for each computing mechanism of a bit slice the multiplexer controls a first slice so that a data stream bit slice is configured to combine a data stream passing through the computing mechanism with a scrambler signal. AN Independent claim is also included for the following: an arrangement for implementing scrambler algorithms in processor-implemented data paths.
机译:该方法包括通过本地多路复用器控制其中包含的位片的每个片中的数据路径,以使得数据路径一方面由四个单元表示,另一方面,对于位片的每种计算机制,多路复用器控制第一切片,使得数据流位切片被配置为将通过计算机制的数据流与加扰器信号进行组合。还包括以下内容的独立权利要求:一种用于在处理器实现的数据路径中实现加扰器算法的装置。

著录项

  • 公开/公告号DE10137458A1

    专利类型

  • 公开/公告日2003-02-20

    原文格式PDF

  • 申请/专利权人 SYSTEMONIC AG;

    申请/专利号DE2001137458

  • 发明设计人 DRESCHER WOLFRAM;

    申请日2001-08-02

  • 分类号H04L9/28;

  • 国家 DE

  • 入库时间 2022-08-21 23:42:44

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