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Field effect transistor memory cell has channel region extending from source to drain region as nano-wire(s) with defect(s) in which charges can be captured/released by voltage applied to gate region
Field effect transistor memory cell has channel region extending from source to drain region as nano-wire(s) with defect(s) in which charges can be captured/released by voltage applied to gate region
The field effect transistor memory cell has source region and a drain region, a channel region and a gate region. The channel region extends from the source region to the drain region and is formed by at least one nano-wire with at least one defect so that charges can be captured and released in the defects by voltage applied to the gate region. Independent claims are also included for the following: (a) a semiconducting memory device with several field effect transistor memory cells (b) and a method of manufacturing one or more field effect transistor memory cells.
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