Cache memory system for network data storage system, comprises memory segment having respective parity segment and data segments

摘要

A cache memory system (16) comprises multiple SDRAM memory boards including respective memory segments. The memory segments are grouped into parity sets having N respective segments containing a parity segment, and N-1 respective data segments. A data value stored in parity segment is calculated by a logical exclusive or operation of data value stored in data segments. An Independent claim is also included for cache memory system usage method.