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manufacturing method of a verdrahtungssubstrates for connecting a chip to a carrier

机译:用于将芯片连接到载体的硅藻土衬底的制造方法

摘要

To develop an interconnecting substrate, to link at least one microchip on a reception substrate, a layer of fusible material (102) is laid on a substrate (100). An initial layer (104) of dielectric material is etched to allow the openings (106) to match the outlet terminals of the interconnecting substrate. Metal pads (108) are formed in the openings (106) to give the outlet terminals, to be covered by a metal layer (110). The metal layer (110) is etched to give the conductive paths (112), overlapping the openings (106) in the dielectric material (104), at least partially, under the metal layer (110). A layer of dielectric material (114) is over the conductive paths, and is etched to give openings at least partially over the conductive paths (112), to be filled with metal pads. The interconnecting substrate is separated by heat, at a temp. equal to or greater than the melting temp. of the fusible layer (102). The dielectric material is of pref. of polyimide.
机译:为了开发互连衬底,以连接接收衬底上的至少一个微芯片,将一层可熔材料(102)放置在衬底(100)上。蚀刻介电材料的初始层(104)以允许开口(106)与互连基板的出口端子匹配。在开口(106)中形成金属垫(108),以提供要由金属层(110)覆盖的出口端子。蚀刻金属层(110)以提供导电路径(112),其至少部分地在金属层(110)下方与电介质材料(104)中的开口(106)重叠。介电材料层(114)在导电路径上方,并且被蚀刻以在导电路径(112)上方至少部分地提供开口,以用金属焊盘填充。在一定温度下,互连衬底被热分离。等于或大于熔化温度。可熔层(102)的一部分。介电材料是优选的。聚酰亚胺。

著录项

  • 公开/公告号DE69630169D1

    专利类型

  • 公开/公告日2003-11-06

    原文格式PDF

  • 申请/专利权人 COMMISSARIAT A LENERGIE ATOMIQUE PARIS;

    申请/专利号DE19966030169T

  • 发明设计人 CAILLAT PATRICE;HENRY DAVID;

    申请日1996-06-27

  • 分类号H01L21/48;H01L21/68;

  • 国家 DE

  • 入库时间 2022-08-21 23:39:22

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