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Under refraction architecture for a computer system with a memory access is not uniform

机译:在折射架构下,具有内存访问权限的计算机系统不统一

摘要

A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.
机译:非统一存储器访问(NUMA)计算机系统包括至少两个通过节点互连耦合的节点,其中至少一个节点包括用于处理中断的处理器。节点被划分为外部中断域,以便始终向发生中断的外部中断域内的处理器提供外部中断。尽管每个外部中断域通常仅包含一个节点,但是可以实现中断通道或中断漏斗以跨节点边界路由外部中断,以呈现给处理器。一旦提供给处理器,中断处理软件便可以在任何处理器上执行以服务外部中断。与现有技术方法相比,通过减少中断处理程序轮询链的大小来加快服务外部中断的速度。除了外部中断之外,本发明的中断体系结构还支持处理器间中断(IPI),通过该处理器间中断,任何处理器都可以中断自身或NUMA计算机系统中的一个或多个其他处理器。通过写入全局系统内存中的内存映射寄存器来触发IPI,这有助于跨节点边界传输IPI,并允许通过向包含要中断的处理器的每个节点传输一个写入事务来简单地触发多播IPI。每个节点内的中断硬件也进行了分配,以实现可伸缩性,其中硬件组件通过跨共享通信路径传送的中断事务进行通信。

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