Power reducing circuit for SRAM arrays used in computer system, has p-type field effect transistors whose drain and source are connected to positive terminals of memory arrays and positive power supply, respectively

摘要

The power reducing circuit has several p-type field effect transistors (PFETs) (PF1-PF8) whose drain, source and gate are electrically connected to positive terminal of memory arrays (MA1-MA4), positive power supply (102) and variable voltage sources, respectively. Independent claims are also included for the following: (1) read and write times decreasing circuit in memory arrays; and (2) read and write times decreasing method in memory arrays.