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High level synthesis method for generating circuit including threads
High level synthesis method for generating circuit including threads
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机译:用于产生包括线程的电路的高级综合方法
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摘要
A high level synthesis method for generating a logic circuit of a register transfer level from an operation description includes a control data flowgraph generation stage; a scheduling stage; an allocation stage; a data path generation stage; and a control logic generation stage. When generating a thread sharing a common memory with another thread operating in parallel therewith, a memory access request is represented by a node of a control data flowgraph so as to perform scheduling, and a control logic is generated. The control logic outputs a memory access request signal to a common memory interface in a state corresponding to a step to which the node is scheduled, and keeps the state until a memory access request acceptance signal from the common memory interface is changed to be active.
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