EVALUATION METHOD FOR CIRCUIT WITH BUILT-IN PLL, EVALUATION SYSTEM FOR CIRCUIT WITH BUILT-IN PLL, AND CIRCUIT WITH BUILT-IN PLL

摘要

PROBLEM TO BE SOLVED: To provide an evaluation method for a circuit with a built-in PLL (Phase Locked Loop), an evaluation system, and a circuit with a built-in PLL, for enhancing the reliability of evaluation results without increasing the number of test patterns.;SOLUTION: A device 42 under test prepares test patterns comprising a combination of an impressed pattern P₁ and an expected pattern which is an output of a normal tested pattern corresponding to the pattern P₁. In synchronization with a system clock, the impressed pattern P₁ is_{outputted from a test device 2, a divider 3 divides the period of the impressed pattern into M/N fold, an impressed pattern P4 divided into M/N fold is inputted into the circuit 4 with a built-in PLL, and an output pattern P3 outputted from the circuit 4 is inputted into the test device 2. The values of M and N are set so that the frequency of the pattern P3 agrees with the frequency of the system clock. The test device 2 evaluates the circuit 4 by collating the output pattern P3 with the expected pattern.;COPYRIGHT: (C)2004,JPO}