Method and system of evaluating PLL built-in circuit

摘要

A method of evaluating a PLL built-in circuit includes outputting an applied pattern signal from a test equipment synchronized with a system clock signal received by the test equipment, dividing the applied pattern signal into M/N frequencies by a frequency divider, wherein M and N are positive integers. The method further includes inputting the divided pattern signal into the PLL built-in circuit, inputting an output pattern signal outputted from the PLL built-in circuit into the test equipment and caring the output pattern signal with the applied pattern signal so as to evaluate the PLL built-in circuit. In the above method, M and N are set in a manner that a frequency of the output pattern signal from the PLL built-in circuit is substantially equal to a frequency of the system clock signal.