Phase-locked loop (PLL) frequency synthesizer (Figure 3), incorporates a fractional spurious compensation circuit. The fractional spurious compensation circuit, it is possible to dynamically compensate the charge pump ripple when the charge pump is operating. Can be employed (324 and 314) phase detector (336), two programmable frequency divider, which uses a charge pump stage pump each of them. By (340), the number of the charge pump that operates on the phase comparison at the time determined fractional accumulator stage. By using a PLL frequency synthesizer, the compensation current trimming is not required. In addition, fractional compensation is dynamic, is less susceptible to environmental changes. It is possible that a phase-locked loop (PLL) fractional-N frequency synthesizer, to incorporate a sample-and-hold circuit. At this frequency synthesizer, I can reduce the circuit size for the loop filter is not necessary. In fractional-N PLL synthesizer or, it is possible to use the phase detector at least two frequency divider and is coupled to the sample-and-hold circuit. Lock detection circuit can first determine the reference voltage of the sample-and-hold circuit.
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