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EMI COUNTERMEASURE CIRCUIT AND EMI COUNTERMEASURE METHOD USED FOR THE SAME

机译:电磁干扰对策电路和用于同一方面的电磁干扰对策方法

摘要

PROBLEM TO BE SOLVED: To provide an EMI countermeasure circuit that has large reduction effect on a disturbing wave and can reduce influence on a clock transmitted through a clock wiring and adjust the reduction effect on the disturbing wave according to the transmission state of the clock wiring and an EMI countermeasure wiring.;SOLUTION: A clock from an oscillation part 1 is inputted to an N-multiplier 3 which multiplies the clock by 1 to N (N: natural number). The clock outputted from the N-multiplier 3 is inputted to a phase shifter 4 which shifts its phase by 0 to 360°. The clock outputted from the phase shifter 4 is inputted to a filter 5 which passes only a necessary frequency band. The clock outputted from the filter 5 is inputted to a gain control part 6 and adjusted there to a necessary amplitude. The clock outputted from the gain control part 6 is inputted to an EMI countermeasure wiring 101 wired in parallel to a clock wire 100 connecting the oscillation part 1 and a clock transmission object 2 together and then transmitted to a terminal part 9 through the EMI countermeasure wiring 101.;COPYRIGHT: (C)2004,JPO
机译:解决的问题:提供一种EMI对策电路,该EMI对策电路对干扰波具有较大的减小效果,并且可以减小对通过时钟配线传输的时钟的影响,并根据时钟配线的传输状态来调整对干扰波的减小效果。解决方案:来自振荡部分1的时钟输入到N乘法器3,该N乘法器3将时钟乘以1到N(N:自然数)。从N乘法器3输出的时钟被输入到移相器4,该移相器4将其相位偏移0至360°。从移相器4输出的时钟输入到仅使必要的频带通过的滤波器5。从滤波器5输出的时钟输入到增益控制部分6,并在那里调节到必要的幅度。从增益控制部分6输出的时钟被输入到EMI对策布线101,该EMI对策布线101与将振荡部分1和时钟传输对象2连接在一起的时钟线100并行布线,然后通过EMI对策布线传输到端子部分9。 101 .;版权:(C)2004,日本特许厅

著录项

  • 公开/公告号JP2004165941A

    专利类型

  • 公开/公告日2004-06-10

    原文格式PDF

  • 申请/专利权人 NEC VIEWTECHNOLOGY LTD;

    申请/专利号JP20020328958

  • 发明设计人 TAKAHASHI RYOJI;

    申请日2002-11-13

  • 分类号H04B15/00;G06F1/04;G06F1/10;H05K9/00;

  • 国家 JP

  • 入库时间 2022-08-21 23:28:14

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