The delay quantitative amendment circuit, the ATM switchboard and delay quantitative amendment manner

摘要

PROBLEM TO BE SOLVED: To realize a delay quantity correction circuit reducing the fluctuation of delay quantity.;SOLUTION: In reception side LSI 12, data transmitted through a transmission line 5 is inputted to a flip flop 7 and clocks transmitted together with the data are inputted to a variable delay circuit 1. The clocks are delayed more in a variable delay circuit 2. The delay quantities of the variable delay circuit 1 and 2 are instructed to become same by a control cirucit 17. A comparator 13 detects a case when the phase of the clock transmitted through the transmission line 5 is not opposite to that of the clock delayed by the variable delay circuit 2. The control circuit 17 judges that the delay quantity of a delay clock is less when output is continuously in an 'H' level four times, judges that the delay quantity of the delay clock is much when output is continuously in an 'L' level four times and changes the delay quantity. The rise edge of the clock comes close to the half of a data change period T and it satisfies the setup holding time of the flip flop. Thus, data can be taken in.;COPYRIGHT: (C)2000,JPO