Processor device and processor control method for executing instruction cache processing for instruction fetch alignment over multiple predictive branch instructions

摘要

An aligned Instruction cache (AIC) containing multiple instruction cache sectors in which may be recorded out-of-sequence blocks of instructions. Basic blocks of instructions are aligned in AIC sectors at program run time. An AIC directory uses the current instruction address to select an AIC directory entry and an associated row in the AIC containing multiple sectors. The AIC directory entry contains multiple "Sector S first address" fields respectively associated with the multiple AIC sectors, each of these directory fields containing the address of the first instruction in the associated AIC sector S when its contents are valid. A "fetch history table" (FHT) contains four FHT entries for each associated AIC row organized in FHT sets of four entries. Each valid FHT entry records a predicted sequence of instructions based on a prior actual execution of the sequence in the same program, which may repeat over and over again. Each FHT entry contains very efficient fields for capturing a previous history of execution for a sequence of blocks of instructions which may be non-sequentially located in memory. Each valid FHT entry can control an outgating of multiple sequences of instructions stored in the sectors of the associated AIC row in a single fetch cycle. Each fetch cycle using a single FHT entry may outgate for execution by the processor a plurality of AIC sectors in any order recorded in the FHT entry, without the processor waiting to fetch these instructions from disparate locations in memory.