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Issue bandwidth in a multi-issue out-of-order processor
Issue bandwidth in a multi-issue out-of-order processor
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机译:多问题无序处理器中的发布带宽
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摘要
A multi-issue microprocessor selectively assigns, with particular emphasis on an particular type of instruction, in a plurality of instructions to various pipelines. The microprocessor maintains counts of the number of instructions assigned to a first pipeline and a second pipeline. Depending on these counts, the processor assigns instructions of the particular type in the plurality of instructions to the first and second pipelines.
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