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Multi-level register bank based configurable etherner frame parser
Multi-level register bank based configurable etherner frame parser
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机译:基于多级寄存器组的可配置以太网帧解析器
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摘要
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of match signals in response to an incoming data signal. Each match signal is generated in response to different search criteria. The second circuit may be configured to present a protocol indication signal in response to the plurality of match signals.
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