首页> 外国专利> Low-bias bottom electrode etch for patterning ferroelectric memory elements

Low-bias bottom electrode etch for patterning ferroelectric memory elements

机译:低偏压底部电极蚀刻,用于构图铁电存储元件

摘要

One aspect of the invention relates to a method of manufacturing FeRAM, and in particular, plasma etching a bottom electrode layer in a ferroelectric capacitor stack. According to the method, plasma etching is carried out at a relatively low bias in an atmosphere that includes a halogen compound and an oxygen source containing carbon, such as carbon monoxide or carbon dioxide. The invention prevents shorting along the sidewalls of the capacitor stack, which can otherwise be caused by re-deposition of material released from the bottom electrode layer. The gas composition and temperature are such that chemical reaction substantially contributes to the etch rate as compared to purely physical etching. In one embodiment, the capacitor stack is etched with a hard mask that include TiAlN and the atmosphere is oxidizing to an extent that increases the selectivity between the hard mask and the bottom electrode layer.
机译:本发明的一个方面涉及一种制造FeRAM的方法,尤其涉及等离子体蚀刻铁电电容器叠层中的底部电极层的方法。根据该方法,在包括卤素化合物和含碳的氧源如一氧化碳或二氧化碳的气氛中以相对低的偏压进行等离子体蚀刻。本发明防止了沿着电容器堆的侧壁的短路,否则这可能是由于从底部电极层释放的材料的重新沉积而引起的。气体成分和温度使得与纯物理蚀刻相比,化学反应实质上有助于蚀刻速率。在一个实施例中,用包括TiAlN的硬掩模蚀刻电容器叠层,并且气氛被氧化到一定程度,从而增加了硬掩模和底部电极层之间的选择性。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号