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Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill
Complementary pass gate logic implementation of 64-bit arithmetic logic unit using propagate, generate, and kill
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机译:使用传播,生成和终止的64位算术逻辑单元的互补通过门逻辑实现
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摘要
An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.
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机译: 在端对端激活f 1 Sub>(00)的“ k”个“最小化区域”结果参数 +1 Sup> m k Sub>中生成的方法 min Sub>→ +1 Sup> m k Sub>用于根据三元数系统的f(+ 1,0,-1)结构的算术公理进行转换模拟信号的参数“«-/ +»[m j Sub>] f(+/-)--”互补代码“转换为条件最小化位置信号的结构模拟信号±< / Sup> [m j Sub>] f усл Sub>(+/-) min Sub>及其实现的功能结构(俄罗斯逻辑版本)