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Modifying a hierarchical representation of a circuit to process features created by interactions between cells
Modifying a hierarchical representation of a circuit to process features created by interactions between cells
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机译:修改电路的分层表示以处理由单元之间的交互作用创建的特征
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摘要
One embodiment of the invention provides a system for analyzing a layout related to a circuit on a semiconductor chip. The system operates by receiving a design hierarchy specifying the layout of the circuit. This layout includes a set of hierarchically organized nodes, wherein a given node specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy. The system operates by modifying the design hierarchy by examining a set of sibling nodes that are located under a parent node in the design hierarchy in order to identify a set of interacting geometrical features between the set of sibling nodes. Next, the system then moves the set of interacting geometrical features to a new child node under the parent node, and then performs an analysis on the modified design hierarchy.
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