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Semiconductor design/fabrication system, semiconductor design/fabrication method and semiconductor design/fabrication program

机译:半导体设计/制造系统,半导体设计/制造方法和半导体设计/制造程序

摘要

A semiconductor design/fabrication system which combines a plurality of function blocks and arranges the combined function blocks on a chip, comprising: a function block selector which selects the function blocks to be arranged on the same chip from a plurality of function blocks for each of which a critical area indicating a range where defective products occur due to existence of defects is known; a chip information calculator which calculates a sum of the critical areas on each of the selected function blocks; an yield calculator which calculates an yield based on a calculation result of the chip information calculator and defect occurrence rate information of a chip fabrication line; a cost delivery time information calculator which calculates information relating to fabrication cost and delivery time of the chip based on a calculation result of the yield calculator and fabrication management information relating to cost and fabrication period of the chip fabrication line; and a combination selector which selects a combination of the function blocks constituting the chip based on the information relating to the fabrication cost and the delivery time of the chip calculated by the cost delivery time information calculator.
机译:一种半导体设计/制造系统,其组合多个功能块并将组合的功能块布置在芯片上,包括:功能块选择器,其从多个功能块中为每个功能块选择要布置在同一芯片上的功能块。已知表示由于存在缺陷而产生缺陷产品的范围的临界区域;芯片信息计算器,计算每个所选功能块上关键区域的总和;成品率计算器,其基于芯片信息计算器的计算结果和芯片制造线的缺陷发生率信息来计算成品率;成本交付时间信息计算器,其基于成品率计算器的计算结果以及与芯片制造线的成本和制造周期有关的制造管理信息,计算与芯片的制造成本和交付时间有关的信息;组合选择器基于成本交货时间信息计算器计算出的与制造成本和芯片交货时间有关的信息,选择构成芯片的功能块的组合。

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