Method and apparatus for testing path delays in a high-speed boundary scan implementation

摘要

A method and apparatus for testing path delays in a high-speed boundary scan implementation overcomes limitations imposed by pipelined high-speed clocking architectures used in integrated circuits. A special phase hold circuit provides a mechanism for clocking circuits undergoing dynamic tests, permitting the dynamic test to produce proper results when the integrated circuit under test is clocked with a high-speed distributed clock. The functional logic clock enable is pipelined to synchronize the functional mode clock with the test mode clock when the tester mode is switched.