Layout pattern verification device for verifying a layout pattern of transistors in the manufacturing of a large scale integrated circuit

摘要

A ROM bit map file indicating placement areas of transistors of a mask ROM is prepared from a layout condition of the transistors in the mask ROM and physical positions of the transistors described in a layout pattern file, a logic simulation is performed by using the ROM bit map file and connection information of the transistors, and the physical positions of the transistors are verified according to a simulation result. Therefore, even though there are a large number of transistors in the mask ROM, the physical positions of the transistors can be reliably verified.