Method and architecture for varying power consumption of a current mode digital/analog converter in proportion to performance parameters

摘要

A method and circuit structure scale the power consumption of a current mode digital/analog converter (DAC) in proportion to performance parameters, such as sampling speed (i.e., clock samples per second) and resolution (number of bits) under programmable control. In one embodiment, a current mode segmented DAC provided approaches the performance of custom implementations designed for specific combinations of these parameters, across a wide range of such parameters by varying current relative to the sampling rate and the resolution and by selectively enabling current sources in the DAC.