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Testing for shorts between interconnect lines in a partially defective programmable logic device
Testing for shorts between interconnect lines in a partially defective programmable logic device
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机译:测试部分有缺陷的可编程逻辑器件中互连线之间的短路
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摘要
Methods of detecting shorts affecting nets of a specified design in a partially defective PLD. The nets participating in the design are identified, along with the interconnect lines used to implement each net. The nets are then divided into two or more groups, where no two nets in a single group can be shorted together by the inadvertent enablement of a single programmable interconnect point between two interconnect lines. The groups are then tested for inadvertent shorts. According to a first aspect of the invention, each group is tested sequentially against all interconnect lines not in the group, or against all nets in other groups. According to another aspect, the groups are tested simultaneously by applying a different stimulus pattern to each group. By comparing a detected value pattern to the stimulus patterns applied to other groups, it can be determined which two groups are participating in the short.
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