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Testing for shorts between interconnect lines in a partially defective programmable logic device

机译:测试部分有缺陷的可编程逻辑器件中互连线之间的短路

摘要

Methods of detecting shorts affecting nets of a specified design in a partially defective PLD. The nets participating in the design are identified, along with the interconnect lines used to implement each net. The nets are then divided into two or more groups, where no two nets in a single group can be shorted together by the inadvertent enablement of a single programmable interconnect point between two interconnect lines. The groups are then tested for inadvertent shorts. According to a first aspect of the invention, each group is tested sequentially against all interconnect lines not in the group, or against all nets in other groups. According to another aspect, the groups are tested simultaneously by applying a different stimulus pattern to each group. By comparing a detected value pattern to the stimulus patterns applied to other groups, it can be determined which two groups are participating in the short.
机译:在部分有缺陷的PLD中检测影响指定设计网的短路的方法。确定参与设计的网络以及用于实现每个网络的互连线。然后将网络分成两组或更多组,其中由于疏忽地启用了两条互连线之间的单个可编程互连点,因此不能将单个组中的两个网短路在一起。然后测试组是否有意外的短裤。根据本发明的第一方面,针对不在该组中的所有互连线或针对其他组中的所有网络,依次测试每个组。根据另一方面,通过对每个组应用不同的刺激模式来同时测试组。通过将检测值模式与应用于其他组的刺激模式进行比较,可以确定哪个组参与了短路。

著录项

  • 公开/公告号US6687884B1

    专利类型

  • 公开/公告日2004-02-03

    原文格式PDF

  • 申请/专利权人 XILINX INC.;

    申请/专利号US20020147732

  • 发明设计人 STEPHEN M. TRIMBERGER;

    申请日2002-05-16

  • 分类号G06R175/00;G01R312/80;

  • 国家 US

  • 入库时间 2022-08-21 23:12:59

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