Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry

摘要

An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.