METHOD TO FORM VERY HIGH MOBILITY VERTICAL CHANNEL TRANSISTOR BY SELECTIVE DEPOSITION OF SIGE OR MULTI-QUANTUM WELLS (MQWS)

摘要

A method of fabricating a vertical channel transistor, comprising thefollowing steps. A semiconductor substrate having an upper surface is provided. Ahigh doped N-type lower epitaxial silicon layer is formed on the semiconductorsubstrate. A low doped P-type middle epitaxial silicon layer is formed on the lowerepitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formedon the middle epitaxial silicon layer. The lower, middle, and upper epitaxial siliconlayers are etched to form a epitaxial layer stack defined by isolation trenches. Oxideis formed within the isolation trenches. The oxide is etched to form a gate trenchwithin one of the isolation trenches exposing a sidewall of the epitaxial layer stackfacing the gate trench. Multi-quantum wells or a stained-layer super lattice isformed on the exposed epitaxial layer stack sidewall. A gate dielectric layer isformed on the multi-quantum wells or the stained-layer super lattice and within thegate trench. A gate conductor layer is formed on the gate dielectric layer, filling thegate trench.