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Apparatus and method for identifying false timing paths in digital circuits
Apparatus and method for identifying false timing paths in digital circuits
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机译:用于识别数字电路中错误的时序路径的设备和方法
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摘要
A method for identifying false paths in a digital circuit. A list of paths corresponding to the digital circuit is either provided or generated. For each path, an AND gate is created. For each element in the path, the off-path signals of the monitor circuits corresponding to the elements of the path are coupled to the input of the AND gate. A plurality of different signals are input to the digital circuit in an attempt to generate a "1" at the output of the AND gate. A false timing path signal is generated for that path if the AND gate does not output a "I" within a pre-determined amount of time. This process is repeated for each path of the digital circuit to identify all false timing paths.
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