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Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries
Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries
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机译:低功耗和高密度D触发器电路实现,特别是对于标准单元库
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摘要
A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section (100) and a slave section (200); the master section comprises a master latch structure (5) and the slave section comprises a slave latch structure (6); the master structure (100) and the slave structure (100) are interposed between a power supply line (VDD) and a ground line (7), and each structure is constituted by a first pair of transistors (8, 9; 12, 13) and by a second pair of transistors (10, 11; 14, 15). The particularity of the invention is that in the master latch structure (5) the transistors (8, 9) the source terminals whereof are connected to the power supply line (VDD) and constitute a first one of the two pairs of transistors (8, 9; 10, 11) are P-channel MOS transistors, the source terminals of the second pair of transistors (10, 11) of the master latch structure (5) are connected to the respective drain terminals of an additional pair of transistors (24, 25), the source terminals whereof are connected to the ground line (7); same-phase clock signals (CK) are fed both to the master section (100) and to the slave section (200).
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