Method of synchronizing a phase-locked loop, phase-locked loop and semiconductor provided with same

摘要

There is provided a method of synchronizing a phase-locked loop (PLL) which is capable of reducing an area occupied by the PLL in a chip of the semiconductor device and shortening a lock-up time even when a band of an oscillation frequency is wide and a changeable range of a multiplying factor is wide.;The method for synchronizing the PLL includes a step of smoothing, by using a low pass filter (14), a control current (I_C) flowing in or out from a charge pump (13, 31, 51, 61) in accordance with an up-clock/UCK or a down-clock DCK to be fed from a phase frequency comparator (11) to output it as a control voltage, a step of oscillating an internal clock (CK_I), by using a voltage controlled oscillator (15), having number of oscillation frequencies corresponding to a control voltage in an oscillation frequency band decided in accordance with oscillation frequency band setting data (DT_F), a step of dividing, using a frequency divider (16), a frequency of the internal clock (CK_I) at a rate of frequency division decided in accordance with multiplying factor setting data (DT_D) to output it as a frequency-divided clock and a step of changing a value of the control current (I_C) in accordance with oscillation frequency band setting data (DT_F) and with multiplying factor setting data (DT_D).