TIMING HIERARCHY COMPRISING DELAYED CLOCK SIGNAL ARRIVAL TIMES FOR PEAK CURRENT REDUCTION

摘要

Disclosed is a method for creating a timing hierarchy in an integrated semiconductor circuit comprising a sequential circuit that is provided with at least two synchronous switching elements with respective timing circuits. The inventive method comprises the following steps: synchronous switching elements having uncritical switching prerequisites regarding a signal arrival time relative to a clock pulse arrival time are determined; the clock pulse arrival time is delayed with the aid of at least one delaying element located in the timing circuit of at least one synchronous switching element having uncritical switching prerequisites so as to minimize the number of synchronous switching elements that simultaneously change the switching mode.