A NOVEL HIGHLY-INTEGRATED FLASH MEMORY AND MASK ROM ARRAY ARCHITECTURE

摘要

A memory device is achieved. The memory device comprises an array of Flash cells (31, 33, 35, 37) and mask ROM cells (32, 34, 36) in a common substrate. Each Flash cell comprises a floating gate, a control gate, a source, a drain, and a channel. Each mask ROM cell comprises a gate, a source, a drain, and a channel. Each source of the mask ROM cells is shared with the Flash cell source. Each electrode of each mask ROM cell gate is coupled to at least one Flash cell control gate. The mask ROM cell gate electrodes comprise a common layer with electrodes of the Flash cell control gates. The mask ROM cells lie in spaces between the Flash cells in the array.