40-GB/S CLOCK AND DATA RECOVERY CIRCUIT IN 0.18 MICROMETERS TECHNOLOGY

摘要

A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de­multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 µm CMOS technology.