ARRANGEMENT FOR REDUCING THE PIEZOELECTRIC EFFECTS IN AT LEAST ONE ELECTRICAL COMPONENT WHICH IS SENSITIVE TO PIEZOELECTRIC EFFECTS AND ARRANGED IN AN ACTIVE LAYER OF SEMICONDUCTOR MATERIAL

摘要

The invention relates to a chip device (1) comprising an active layer of semiconductor material (2) which is divided into a first area (2a) having an electrical component (3) which is sensitive to piezoelectric effects, and a second area (2b) with a plurality of contacts (6) used for electrical contacting. The invention aims to reduce the piezoelectric effects in the electrical component (3) which is sensitive to said effects. In order to achieve this, the active layer of semiconductor material (2) is connected to a substrate (5) exclusively in the area (2b) of the contacts (6) by means of an electrical contact material, said connection being mechanical and electrical and/or thermal. The area (2a) containing the electrical component (3) which is sensitive to piezoelectric effects is disposed at a distance from the substrate (5) and is free from the electrical contact material.